S. VenkataKeerthy

Department of Computer Science and Engineering. Indian Institute of Technology Hyderabad.

I am a doctoral student in the Department of Computer Science and Engineering at IITH, advised by Dr. Ramakrishna Upadrasta. I am part of the Scalable Compilers for Heterogeneous Architectures group.

I received B.Tech in Information Technology from SASTRA University in 2016. Previously, I was working as an Associate Software Engineer at Symantec (now Norton Lifelock), Chennai.

Research Interests

My broad area of research interest is in the intersection of programming languages and machine learning.

In particular, I am interested in designing program embeddings that encode the program analysis information by using representation learning methods. In my opinion, this problem can be seen as part of efforts to strengthen in making AI understand programs. Such embeddings are helpful in two broad areas – performance optimizations in compilers and program comprehensions for various software engineering applications that are either hard or undecidable. I focus on modeling the non-trivial problems of these domains that follow heuristics as machine learning problems that preserve semantic correctness.

In the longer term, I look forward to developing an ML-based compiler optimization pipeline, where the optimization decisions are driven by machine learning models that work cooperatively to improve performance.

Recent activities

Feb 25, 2024 Our work, “The Next 700 ML-Enabled Compiler Optimizations” gets accepted in CC 2024. (code) I will also be presenting variations of ML-Compiler-Bridge in LLVM-CGO and C4ML workshops.
Dec 1, 2023 New pre-print: VEXIR2Vec: An Architecture-Neutral Embedding Framework for Binary Similarity
Oct 10, 2023 Presenting “Experiments on different ML-Compiler Communication approaches” in ML-Guided Compiler Optimization Workshop, LLVM Developers’ Meeting.
May 5, 2023 Presenting a technical talk “ML-LLVM-Tools: Towards Seamless Integration of Machine Learning in Compiler Optimizations” in EuroLLVM Developers’ Meeting.
Dec 21, 2022 Our presentation “GeMS: Generating Millions of SCoPs” gets accepted in IMPACT 2023.
Dec 20, 2022 RL4ReAl gets accepted in CC 2023 :sparkles:
Sep 9, 2022 Our work “Reinforcement Learning assisted Loop Distribution for Locality and Vectorization” is accepted in LLVM-HPC 2022.
May 3, 2022 Our paper “Packet Processing Algorithm Identification using Program Embeddings” got accepted in APNET 2022
Apr 6, 2022 New pre-print: RL4ReAl: Reinforcement Learning for Register Allocation
Mar 18, 2022 Our work “POSET-RL: Phase ordering for Optimizing Size and Execution Time using Reinforcement Learning” got accepted in ISPASS 2022. This will also be presented in the LLVM Performance Workshop at CGO 2022.

Please see here for all activities...

Selected Publications

  1. IR2Vec: LLVM IR Based Scalable Program Embeddings
    VenkataKeerthy, S., Aggarwal, R., Jain, S., Desarkar, M. S., Upadrasta, R., and Srikant, Y. N.
    ACM Trans. Archit. Code Optim. 2020
  2. P4LLVM: An LLVM Based P4 Compiler
    Dangeti, T. K.*, VenkataKeerthy, S.*, and Upadrasta, R.
    In P4WE workshop, International Conference on Network Protocols (ICNP) 2018
  3. RL4ReAl: Reinforcement Learning for Register Allocation
    VenkataKeerthy, S., Jain, S., Aggarwal, R., Cohen, A., and Upadrasta, R.
    arXiv 2022