S. VenkataKeerthy

Selected Publications

1. IR2Vec: LLVM IR Based Scalable Program Embeddings

   VenkataKeerthy, S., Aggarwal, R., Jain, S., Desarkar, M. S., Upadrasta, R., and Srikant, Y. N.

   ACM Trans. Archit. Code Optim. 2020

   Abs arXiv Code Website Talk Cite

   We propose IR2VEC, a Concise and Scalable encoding infrastructure to represent programs as a distributed embedding in continuous space. This distributed embedding is obtained by combining representation learning methods with flow information to capture the syntax as well as the semantics of the input programs. As our infrastructure is based on the Intermediate Representation (IR) of the source code, obtained embeddings are both language and machine independent. The entities of the IR are modeled as relationships, and their representations are learned to form a seed embedding vocabulary. Using this infrastructure, we propose two incremental encodings: Symbolic and Flow-Aware. Symbolic encodings are obtained from the seed embedding vocabulary, and Flow-Aware encodings are obtained by augmenting the Symbolic encodings with the flow information. We show the effectiveness of our methodology on two optimization tasks (Heterogeneous device mapping and Thread coarsening). Our way of representing the programs enables us to use non-sequential models resulting in orders of magnitude of faster training time. Both the encodings generated by IR2VEC outperform the existing methods in both the tasks, even while using simple machine learning models. In particular, our results improve or match the state-of-the-art speedup in 11/14 benchmark-suites in the device mapping task across two platforms and 53/68 benchmarks in the thread coarsening task across four different platforms. When compared to the other methods, our embeddings are more scalable, is non-data-hungry, and has better Out-Of-Vocabulary (OOV) characteristics.

   @article{VenkataKeerthy-2020-IR2Vec,
     author = {VenkataKeerthy, S. and Aggarwal, R. and Jain, S. and Desarkar, M. S. and Upadrasta, R. and Srikant, Y. N.},
     title = {{IR2Vec: LLVM IR Based Scalable Program Embeddings}},
     year = {2020},
     issue_date = {December 2020},
     publisher = {Association for Computing Machinery},
     address = {New York, NY, USA},
     volume = {17},
     number = {4},
     issn = {1544-3566},
     url = {https://doi.org/10.1145/3418463},
     doi = {10.1145/3418463},
     journal = {ACM Trans. Archit. Code Optim.},
     month = dec,
     articleno = {32},
     numpages = {27},
     keywords = {heterogeneous systems, representation learning, compiler optimizations, LLVM, intermediate representations},
     arxiv = {1909.06228},
     code = {https://github.com/IITH-Compilers/IR2Vec},
     website = {https://compilers.cse.iith.ac.in/projects/ir2vec/},
     talk = {https://www.youtube.com/watch?v=kyD4ysn8ljE&t=4685s},
     selected = {true}
   }
   

2. P4LLVM: An LLVM Based P4 Compiler

   Dangeti, T. K.^*, VenkataKeerthy, S.^*, and Upadrasta, R.

   In P4WE workshop, International Conference on Network Protocols (ICNP) 2018

   Abs HTML Code Slides Cite

   We propose P4LLVM, an LLVM based P4 compiler for achieving better optimizations to improve the runtime performance of the network. The front-end of P4LLVM converts P4-16’s code to LLVM’s Intermediate Representation (IR). This IR is passed through various optimizations of LLVM and is translated to JSON for targeting a BMV2 Switch. We show the performance improvements obtained by running LLVM optimization passes in P4LLVM when compared to P4C.

   @inproceedings{Dangeti-2018-p4llvm,
     title = {{P4LLVM: An LLVM Based P4 Compiler}},
     author = {Dangeti, T. K.* and VenkataKeerthy, S.* and Upadrasta, R.},
     booktitle = {{P4WE workshop, International Conference on Network Protocols (ICNP)}},
     year = {2018},
     code = {https://github.com/IITH-Compilers/P4LLVM},
     html = {https://ieeexplore.ieee.org/document/8526847},
     slides = {https://p4.org/assets/P4WE_2018/Dangeti_Kumar.pdf},
     selected = {true}
   }
   

3. RL4ReAl: Reinforcement Learning for Register Allocation

   VenkataKeerthy, S., Jain, S., Aggarwal, R., Cohen, A., and Upadrasta, R.

   arXiv 2022

   Abs arXiv Cite

   We propose a novel solution for the Register Allocation problem, leveraging multi-agent hierarchical Reinforcement Learning. We formalize the constraints that precisely define the problem for a given instruction-set architecture, while ensuring that the generated code preserves semantic correctness. We also develop a gRPC based framework providing a modular and efficient compiler interface for training and inference. Experimental results match or outperform the LLVM register allocators, targeting Intel x86 and ARM AArch64.

   @article{venkatakeerthy2022rl4real,
     title = {RL4ReAl: Reinforcement Learning for Register Allocation},
     author = {VenkataKeerthy, S. and Jain, S. and Aggarwal, R. and Cohen, A. and Upadrasta, R.},
     journal = {arXiv},
     year = {2022},
     eprint = {2204.02013},
     archiveprefix = {arXiv},
     primaryclass = {cs.LG},
     selected = {true},
     arxiv = {2204.02013}
   }